The present invention relates generally to call processor architectures, and in particular to methods and apparatus for high-availability call processor systems and methods.
Conventional call processor systems use special purpose, dedicated systems for implementing redundancy. For example, some conventional systems utilize two computer systems, one of which is active and the other standby, and special purpose hardware and software that interacts with each computer system to implement high-availability. The special purpose hardware and software communicates with the active computer system to capture status information so that in the event the active system goes down the standby system can start in place of the active system using the information collected by the special purpose hardware and software.
Thus, conventional high-availability architectures require special purpose hardware and software, which raises system costs. The additional costs make systems very expensive. There is, therefore, a need for a high-availability architecture that solves the problems associated with special purpose hardware and software high-availability systems.
The call processor system consistent with the invention takes advantage of commercial off the shelf (COTS) products while maintaining high availability. The call processor system is comprised of four main components: X86 Single Board Compute Platform (CP PII), System Area Network (SAN) interface, high-speed pipes (HSP""s), System Utility Card (SU), and a Core to Network Interface Card (cCNI).
The compact peripheral component interconnect (cPCI) standard specifies both the packaging, format and the electrical interface for the back plane and the on card bus structure of the system. The cPCI standard also include the hotswap specification. The hot swap specification has standardized a way to insert and remove circuit packs in a live system without affecting other circuit packs that share the same bus. The specification also specifies how an operating system (OS) can be notified so as to allow dynamic loading of drivers.
By using COTS components, future upgrades to newer technologies are easy and quick, thus leveraging the time to market opportunities that can be gained by using, third party off the shelf components. The system implements a high-availability architecture based around a system area networks (SAN) technology that allows the call processor to perform better than conventional systems, and also build a system that could easily evolve. The system features include a 1+1 sparing strategy, graceful switchover that preserves all call states, ungraceful switchover in case of node failure that would preserve all existing, established calls, hard disk drive redundancy, and IP take over (the system presents a logical Ethernet connection to the OAandM connection). The system addresses all of these issues and in addition provides for querying the health of the inactive side at any time. Due to the high bandwidth of new high-speed network interface cards, the complete system memory image can be transferred to the inactive system on command within one second; this type of performance allows the active processor to run asynchronously to the standby system, allowing significant performance gains to be achieved on the active side. When a graceful switchover is required, the complete system state of the active processor can be transferred to the standby processor allowing the standby processor to continue as if it had been in control all the time. This strategy works well for hardware failure.